This invention relates to a data processing system having a microprocessor and coprocessors and more particularly to a data processing system suitable for closely coupled coprocessors (CP's) to a microprocessor (MPU).
A 16-bit or 32-bit microprocessor system is used in association with a coprocessor such as a floating point unit (FPU) to speed up numeric operations and so on. Accordingly, how to couple the CP to the MPU has been studied and some systems have been proposed.
In the past, three systems have been announced as referred to in the description of the prior art of JP-A-59-201154, which contemplates a fourth system as novel one. The first system, as explained in JP-A-59-201154, employs an Intel 8087 numeric data processor which monitors the instruction of an Intel 8086 processor to search for the instruction for a CP. To implement the first system, the CP requires an internal hardware arrangement which enables the CP to trace an instruction queue of an MPU. The second system, as disclosed in JP-A-59-20ll54, also needs the additional provision of internal hardware of a CP as in the case of the first system.
The third system, as disclosed in JP-59-201154, a CP for a National Semiconductor NS 16000, can eliminate the doubling of hardware is a slave unit to the MPU and data transfer between the CP and a memory is performed only through the MPU.
Finally, JP-A-59-20ll54 shows that the fourth system can eliminate the doubling of hardware and signals dedicated to a CP as well so that execution of instructions by the CP may be adjustable. But, as shown in FIGS. 14 and 15 of JP-A-59-201154, data transfer between the CP and a memory is again performed through a MPU.
When considering the operation speed of the conventional FPU, a Motorola MC 68881, for example, takes 5.8 .mu.s (16.67 MHz) for multiplication of 64-bit floating point as described in the Motorola Semiconductor News No. 11 published in May, 1985. Therefore, overhead of the interface between MPU and FPU in the system of JP-A-59-201154 is not so large as to be incompatible with the operation speed and hence the interface between MPU and FPU of the above publication directed to general purposes may be considered meritorious.
Progressive advance in semiconductor technology however leads to realization of logical circuits such as multipliers with integrated circuits and there is a tendency toward improving the ability of the FPU to have an operation speed of about 180 ns even for 64-bit floating point multiplication as described in Digest of ISSCC, 1985, pp. 16-17.
When such a high-operation-speed FPU is incorporated in the system of the aforementioned publication, overhead of the interface becomes larger than the operation time and the effects of the high operation speed of the FPU are diluted, indicating that the system is insufficient for coupling with the high-operation-speed FPU.
Where the high-operation-speed FPU is incorporated into the first and second systems, the data transfer between FPU and memory can be performed within one bus cycle but the internal hardware of the CP not participating in operations essential to the FPU occupies the integration space, leaving behind insufficient space for a high-operation-speed FPU integration.
In the third and fourth coprocessor systems, on the other hand, because of the data transfer between FPU and memory performed through the MPU, two bus cycles are required and speed-up of the FPU is difficult to lead to improved performance of the entire system.